1. Field of the Invention
The invention relates to the fabrication of integrated circuits and to a process for depositing dielectric layers on a substrate and the structures formed by the dielectric layer.
2. Description of the Related Art
One of the primary steps in the fabrication of modern semiconductor devices is the formation of metal and dielectric layers on a substrate by chemical reaction of gases. Such deposition processes are referred to as chemical vapor deposition or CVD. Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired layer.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices that will fit on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.35 μm and even 0.18 μm feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries.
To further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and to use insulators having low dielectric constants (dielectric constant (k)<4.0) to also reduce the capacitive coupling between adjacent metal lines. One such low k material is silicon oxycarbide deposited by a chemical vapor deposition process and silicon carbide, both of which may be used as dielectric materials in fabricating damascene features.
One conductive material having a low resistivity is copper and its alloys, which have become the materials of choice for sub-quarter-micron interconnect technology because copper has a lower resistivity than aluminum, (1.7 μΩ-cm compared to 3.1 μΩ-cm for aluminum), a higher current and higher carrying capacity. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
One difficulty in using copper in semiconductor devices is that copper is difficult to etch and achieve a precise pattern. Etching with copper using traditional deposition/etch processes for forming interconnects has been less than satisfactory. Therefore, new methods of manufacturing interconnects having copper containing materials and low k dielectric materials are being developed.
One method for forming vertical and horizontal interconnects is by a damascene or dual damascene method. In the damascene method, one or more dielectric materials, such as the low k dielectric materials, are deposited and pattern etched to form the vertical interconnects, e.g., vias, and horizontal interconnects, e.g., lines. Conductive materials, such as copper containing materials, and other materials, such as barrier layer materials used to prevent diffusion of copper containing materials into the surrounding low k dielectric, are then inlaid into the etched pattern. Any excess copper containing materials and excess barrier layer material external to the etched pattern, such as on the field of the substrate, is then removed.
However, when low k material have been used in damascene formation, it has been difficult to produced features with little or no surface defects or feature deformation. It as been observed that low k dielectric materials are often porous and susceptible to being scratched and damaged during removal of conductive materials, which results in surface defects being formed on the substrate surface. Further, low k materials are often brittle and may deform under conventional polishing processes. One solution to limiting or reducing surface defects and deformation is to deposit a hardmask over the exposed low k materials prior to patterning and etching feature definitions in the low k materials. The hardmask is resistive to damage and deformation. The hardmask protects the underlying low k materials during subsequent material deposition and planarization or material removal processes, such as chemical mechanical polishing techniques or etching techniques, to reduce defect formation and feature deformation. The hardmask may then be removed following planarization prior to subsequent processing of the substrate.
One material of interest as a hardmask is amorphous carbon. Amorphous carbon has a low dielectric constant (i.e., k<4) and a sufficiently high resistance to removal from etching and polishing techniques to perform as a hardmask. However, hardmask removal processes comprise plasma-stripping processes containing oxygen, etching gases, such as CF4, and inert gases. The underlying low k material is sensitive to damage from etching gases and inert gases during the stripping processes and is sensitive to oxygen contamination, which may result in surface defects in the underlying low k material as well as an increase in the dielectric constant of the low k material from oxygen contamination. Thus, such hardmask removal processes have been observed to produce dielectric stacks having a higher than desired dielectric constant.
Therefore, there remains a need for an improved process for depositing and removing layers disposed on low k dielectric materials with minimal effect of dielectric constants.